For decades, the semiconductor industry has been driven by the tenacious pursuit to double the number of components on a single die every two years. Motivated by simple economics, this unrelenting pursuit of density scaling fueled the exponential growth of the industry. As technology continues to scale, however, it is apparent that power dissipation and density limits are already slowing further improvements with CMOS, and the cost of full-custom design and manufacturing is becoming prohibitive. While there are various post-CMOS technology candidates, it is likely that future integrated systems will be based on a myriad of technologies that are packaged and/or stacked together. The combination of circuits and technologies will be determined by the target application, cost, and required performance.
Nanoscale magnetic devices, such as STT memory devices [see J.-G. Zhu, “Magnetoresistive Random Access Memory: The Path to Competitiveness and Scalability,” (Invited Paper) Proceedings of the IEEE, vol. 96, 11, pp. 1786-1798 (2008)], are particularly promising devices for on-chip non-volatile storage. These devices can provide a “disk-like” storage capability for an integrated system while operating at low power levels.
Various attempts and ideas appear in the prior art regarding the possibility of using spin-based magnetic devices as logic switching devices. See e.g., the following references:    1. S. Bandyopadhyay, et al., “Electron spin for classical information processing: a brief survey of spin-based logic devices, gates and circuits,” Nanotechnology, v. 20 (2009), pp. 1-35.    2. B. Behin-Aein, et al., “Proposal for an all-spin logic device with built-in memory,” Nature Nanotechnology, vol. 5 (2010), pp. 266-270.    3. D. A. Allwood, et al., “Magnetic domain-wall logic,” Science, v. 309 (2005), pp. 1688-1692.    4. C. Chappert, et al., “The emergence of spin electronics in data storage,” Nature Materials, v. 6 (2007), pp. 813-823.    5. B. Dieny, et al., “Spin-transfer effect and its use in spintronic components,” Int. J. of Nanotechnology, Vol. 7, Nos. 4/5/6/7/8 (2010), pp. 591-614.    6. S. Fukami, et al., “Low-Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM,” 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 230-31.    7. X. F. Han, et al., “Nano-Scale Patterned Magnetic Tunnel Junction and Its Device Applications,” AAPPS Bulletin, v. 18, n. 6 (2008), pp. 24-32.    8. R. K. Kawakami, et al., “Fundamentals of Spintronics in Metal and Semiconductor Systems,” in A. Korkin and F. Rosei (eds.), Nanoelectronics and Photonics, Springer (2008), pp. 59-114.    9. J.-P. Nozieres, et al., U.S. Pat. No. 7,518,897 B2, “System and method for providing content-addressable magnetoresistive random access memory cells,” (2009).    10. C. Pampuch, et al., “Programmable magnetologic full adder,” Applied Physics A, v. 79 (2004), pp. 415-16.    11. G. Reiss, et al., “Magnetic Tunnel Junctions,” Springer (2007), pp. 291-333.    12. M. B. Johnson, U.S. Pat. No. 7,209,381 B2, “Signal Processing Device with Disparate Magnetoelectronic Gates” (2007).    13. J. Shen, “Logic Devices and Circuits Based on Giant Magnetoresistance,” IEEE Trans. on Magnetics, v. 33, n. 6 (1997), pp. 492-97.    14. H. Shin, PCT Pat. App. No. WO 2009/011,484 A1, “Magnetic Memory Cell.”    15. H. Shin, et al., PCT Pat. App. No. WO 2009/104851 A1, “Device for XOR Magneto-Logic Circuit using STT-MTJ.”    16. L. G. Chua-Eoan, PCT Pat. App. No. WO 2010/019881 A1, “Gate Level Reconfigurable Magnetic Logic.”    17. P. Xu, et al., “An all-metallic logic gate based on current-driven domain wall motion,” Nature Nanotechnology, v. 3 (2008).    18. M. Yamanouchi, et al., “Current-induced domain-wall switching in a ferromagnetic semiconductor structure,” Nature, v. 428 (2004), pp. 539-542.    19. H. Zabel, “Progress in spintronics,” Superlattices and Microstructures, v. 46 (2009), pp. 541-553.    20. W. Zhao, et al., “New non-volatile logic based on spin-MTJ,” Physica Status Solidi (a), v. 205, n. 6 (2008), pp. 1373-77.These references—which are incorporated for their teachings of various details regarding the physical principles on which aspects of the invention operate, as well as additional descriptions of various structures, elements, materials, and devices useful in the construction or application of various embodiments of the invention, as well as various fabrication techniques suitable for use in fabricating embodiments of the invention, or portions thereof—demonstrate a significant, worldwide effort to develop commercially viable magnetic logic devices over the past decade. Nevertheless, as persons skilled in the art acknowledge, this goal has not yet been achieved. See, e.g., Bandyopadhyay, et al. (2009), p. 32 (“In this review, we have attempted to provide a synopsis of our current understanding of those spin-based logic devices, gates and architectures that have attracted the most attention in the engineering and applied physics community. We have found that no spin-based approach is perfect; all have serious shortcomings.”); R. K. Kawakami, et al. (2008), p. 63 (“Finally, spintronics has the possibility to deliver high-speed performance and low power consumption, although one should be cautious about making such blanket statements . . . . To sum up, there is potential for high-speed, low-power applications, but novel circuit architectures need to be developed to bring this to fruition.”).